Synthesis Messages

Report Title GowinSynthesis Report
Design File D:\Elektronik\Gowin\HDL\TangPrimer25K\Kopplerauswertung V1.0\src\fifo_sc_top\temp\FIFO_SC\fifo_sc_define.v
D:\Elektronik\Gowin\HDL\TangPrimer25K\Kopplerauswertung V1.0\src\fifo_sc_top\temp\FIFO_SC\fifo_sc_parameter.v
C:\Program Files\Gowin\Gowin_V1.9.11.01_Education_x64\IDE\ipcore\FIFO_SC\data\edc_sc.v
C:\Program Files\Gowin\Gowin_V1.9.11.01_Education_x64\IDE\ipcore\FIFO_SC\data\fifo_sc.v
C:\Program Files\Gowin\Gowin_V1.9.11.01_Education_x64\IDE\ipcore\FIFO_SC\data\fifo_sc_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.11.01 Education (64-bit)
Part Number GW5A-LV25MG121NC1/I0
Device GW5A-25
Device Version A
Created Time Mon Jun 29 17:50:13 2026
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module fifo_sc_top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.421s, Elapsed time = 0h 0m 0.439s, Peak memory usage = 41.496MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 41.496MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 41.496MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 41.496MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 41.496MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 41.496MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 41.496MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 41.496MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 41.496MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 41.496MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 41.496MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 41.496MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.187s, Elapsed time = 0h 0m 0.227s, Peak memory usage = 56.211MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.054s, Peak memory usage = 56.211MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 56.211MB
Total Time and Memory Usage CPU time = 0h 0m 0.638s, Elapsed time = 0h 0m 0.738s, Peak memory usage = 56.211MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 22
I/O Buf 22
    IBUF 12
    OBUF 10
Register 20
    DFFPE 1
    DFFCE 19
LUT 41
    LUT2 11
    LUT3 8
    LUT4 22
ALU 8
    ALU 8
BSRAM 1
    SDPB 1

Resource Utilization Summary

Resource Usage Utilization
Logic 49(41 LUT, 8 ALU) / 23040 <1%
Register 20 / 23280 <1%
  --Register as Latch 0 / 23280 0%
  --Register as FF 20 / 23280 <1%
BSRAM 1 / 56 2%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 Clk Base 10.000 100.000 0.000 5.000 Clk_ibuf/I

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 Clk 100.000(MHz) 212.483(MHz) 6 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 5.294
Data Arrival Time 5.017
Data Required Time 10.311
From fifo_sc_inst/Empty_s0
To fifo_sc_inst/Empty_s0
Launch Clk Clk[R]
Latch Clk Clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 Clk
0.000 0.000 tCL RR 1 Clk_ibuf/I
0.000 0.000 tINS RR 22 Clk_ibuf/O
0.375 0.375 tNET RR 1 fifo_sc_inst/Empty_s0/CLK
0.757 0.382 tC2Q RR 5 fifo_sc_inst/Empty_s0/Q
1.132 0.375 tNET RR 1 fifo_sc_inst/rbin_next_2_s4/I0
1.659 0.526 tINS RR 10 fifo_sc_inst/rbin_next_2_s4/F
2.034 0.375 tNET RR 1 fifo_sc_inst/rbin_next_2_s3/I0
2.560 0.526 tINS RR 2 fifo_sc_inst/rbin_next_2_s3/F
2.935 0.375 tNET RR 2 fifo_sc_inst/n125_s0/I0
3.491 0.556 tINS RF 1 fifo_sc_inst/n125_s0/COUT
3.491 0.000 tNET FF 2 fifo_sc_inst/n126_s0/CIN
3.541 0.050 tINS FR 1 fifo_sc_inst/n126_s0/COUT
3.541 0.000 tNET RR 2 fifo_sc_inst/n127_s0/CIN
3.591 0.050 tINS RR 1 fifo_sc_inst/n127_s0/COUT
3.591 0.000 tNET RR 2 fifo_sc_inst/n128_s0/CIN
3.641 0.050 tINS RR 1 fifo_sc_inst/n128_s0/COUT
3.641 0.000 tNET RR 2 fifo_sc_inst/n129_s0/CIN
3.691 0.050 tINS RR 1 fifo_sc_inst/n129_s0/COUT
3.691 0.000 tNET RR 2 fifo_sc_inst/n130_s0/CIN
3.741 0.050 tINS RR 1 fifo_sc_inst/n130_s0/COUT
4.116 0.375 tNET RR 1 fifo_sc_inst/rempty_val_s1/I0
4.642 0.526 tINS RR 1 fifo_sc_inst/rempty_val_s1/F
5.017 0.375 tNET RR 1 fifo_sc_inst/Empty_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 Clk
10.000 0.000 tCL RR 1 Clk_ibuf/I
10.000 0.000 tINS RR 22 Clk_ibuf/O
10.375 0.375 tNET RR 1 fifo_sc_inst/Empty_s0/CLK
10.311 -0.064 tSu 1 fifo_sc_inst/Empty_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.385, 51.373%; route: 1.875, 40.388%; tC2Q: 0.382, 8.239%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 2

Path Summary:
Slack 5.574
Data Arrival Time 4.737
Data Required Time 10.311
From fifo_sc_inst/Empty_s0
To fifo_sc_inst/Full_s0
Launch Clk Clk[R]
Latch Clk Clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 Clk
0.000 0.000 tCL RR 1 Clk_ibuf/I
0.000 0.000 tINS RR 22 Clk_ibuf/O
0.375 0.375 tNET RR 1 fifo_sc_inst/Empty_s0/CLK
0.757 0.382 tC2Q RR 5 fifo_sc_inst/Empty_s0/Q
1.132 0.375 tNET RR 1 fifo_sc_inst/rbin_next_2_s4/I0
1.659 0.526 tINS RR 10 fifo_sc_inst/rbin_next_2_s4/F
2.034 0.375 tNET RR 1 fifo_sc_inst/rbin_next_6_s4/I0
2.560 0.526 tINS RR 1 fifo_sc_inst/rbin_next_6_s4/F
2.935 0.375 tNET RR 1 fifo_sc_inst/wfull_val_s1/I0
3.461 0.526 tINS RR 1 fifo_sc_inst/wfull_val_s1/F
3.836 0.375 tNET RR 1 fifo_sc_inst/wfull_val_s0/I0
4.362 0.526 tINS RR 1 fifo_sc_inst/wfull_val_s0/F
4.737 0.375 tNET RR 1 fifo_sc_inst/Full_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 Clk
10.000 0.000 tCL RR 1 Clk_ibuf/I
10.000 0.000 tINS RR 22 Clk_ibuf/O
10.375 0.375 tNET RR 1 fifo_sc_inst/Full_s0/CLK
10.311 -0.064 tSu 1 fifo_sc_inst/Full_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 2.105, 48.252%; route: 1.875, 42.980%; tC2Q: 0.382, 8.768%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 3

Path Summary:
Slack 7.376
Data Arrival Time 2.935
Data Required Time 10.311
From fifo_sc_inst/Empty_s0
To fifo_sc_inst/rbin_8_s0
Launch Clk Clk[R]
Latch Clk Clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 Clk
0.000 0.000 tCL RR 1 Clk_ibuf/I
0.000 0.000 tINS RR 22 Clk_ibuf/O
0.375 0.375 tNET RR 1 fifo_sc_inst/Empty_s0/CLK
0.757 0.382 tC2Q RR 5 fifo_sc_inst/Empty_s0/Q
1.132 0.375 tNET RR 1 fifo_sc_inst/rbin_next_2_s4/I0
1.659 0.526 tINS RR 10 fifo_sc_inst/rbin_next_2_s4/F
2.034 0.375 tNET RR 1 fifo_sc_inst/rbin_next_8_s2/I0
2.560 0.526 tINS RR 3 fifo_sc_inst/rbin_next_8_s2/F
2.935 0.375 tNET RR 1 fifo_sc_inst/rbin_8_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 Clk
10.000 0.000 tCL RR 1 Clk_ibuf/I
10.000 0.000 tINS RR 22 Clk_ibuf/O
10.375 0.375 tNET RR 1 fifo_sc_inst/rbin_8_s0/CLK
10.311 -0.064 tSu 1 fifo_sc_inst/rbin_8_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 1.053, 41.113%; route: 1.125, 43.946%; tC2Q: 0.382, 14.941%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 4

Path Summary:
Slack 7.376
Data Arrival Time 2.935
Data Required Time 10.311
From fifo_sc_inst/Empty_s0
To fifo_sc_inst/rbin_7_s0
Launch Clk Clk[R]
Latch Clk Clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 Clk
0.000 0.000 tCL RR 1 Clk_ibuf/I
0.000 0.000 tINS RR 22 Clk_ibuf/O
0.375 0.375 tNET RR 1 fifo_sc_inst/Empty_s0/CLK
0.757 0.382 tC2Q RR 5 fifo_sc_inst/Empty_s0/Q
1.132 0.375 tNET RR 1 fifo_sc_inst/rbin_next_2_s4/I0
1.659 0.526 tINS RR 10 fifo_sc_inst/rbin_next_2_s4/F
2.034 0.375 tNET RR 1 fifo_sc_inst/rbin_next_7_s4/I0
2.560 0.526 tINS RR 2 fifo_sc_inst/rbin_next_7_s4/F
2.935 0.375 tNET RR 1 fifo_sc_inst/rbin_7_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 Clk
10.000 0.000 tCL RR 1 Clk_ibuf/I
10.000 0.000 tINS RR 22 Clk_ibuf/O
10.375 0.375 tNET RR 1 fifo_sc_inst/rbin_7_s0/CLK
10.311 -0.064 tSu 1 fifo_sc_inst/rbin_7_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 1.053, 41.113%; route: 1.125, 43.946%; tC2Q: 0.382, 14.941%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%

Path 5

Path Summary:
Slack 7.376
Data Arrival Time 2.935
Data Required Time 10.311
From fifo_sc_inst/Empty_s0
To fifo_sc_inst/rbin_6_s0
Launch Clk Clk[R]
Latch Clk Clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 Clk
0.000 0.000 tCL RR 1 Clk_ibuf/I
0.000 0.000 tINS RR 22 Clk_ibuf/O
0.375 0.375 tNET RR 1 fifo_sc_inst/Empty_s0/CLK
0.757 0.382 tC2Q RR 5 fifo_sc_inst/Empty_s0/Q
1.132 0.375 tNET RR 1 fifo_sc_inst/rbin_next_2_s4/I0
1.659 0.526 tINS RR 10 fifo_sc_inst/rbin_next_2_s4/F
2.034 0.375 tNET RR 1 fifo_sc_inst/rbin_next_6_s5/I0
2.560 0.526 tINS RR 2 fifo_sc_inst/rbin_next_6_s5/F
2.935 0.375 tNET RR 1 fifo_sc_inst/rbin_6_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 Clk
10.000 0.000 tCL RR 1 Clk_ibuf/I
10.000 0.000 tINS RR 22 Clk_ibuf/O
10.375 0.375 tNET RR 1 fifo_sc_inst/rbin_6_s0/CLK
10.311 -0.064 tSu 1 fifo_sc_inst/rbin_6_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 3
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%
Arrival Data Path Delay: cell: 1.053, 41.113%; route: 1.125, 43.946%; tC2Q: 0.382, 14.941%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.375, 100.000%